While today's telecommunication transmission networks rely mainly on optical transmission, internal signal processing in the network elements of a transmission network is still electrical in most cases.
The recent definition of the multiplexing principles and bitrates of an Optical Transport Network (ITU-T G.709) introduces a three level hierarchy with bitrates of 2,7 Gbit/s, 10,7 Gbit/s and 43 Gbit/s. Therefore, equipment is required for electrically processing these high bitrate signals. In particular, a need exists for an optical crossconnect for establishing cross-connections in an optical transport network. An optical crossconnect is a type of switch with a huge number of I/O ports allowing to establish semi-permanent connections from any to any of these I/O ports. Internally, most optical crossconnects operate electrically, as all-optical switching still provides a number of drawbacks and envolves certain system limitations. An optical crossconnect, internally operating electrically, has thus to switch a number of asynchronous electrical signals at different bitrates from any input to any output port. This requires large scale integrated electrical switching matrices for switching high bitrate electrical signals in space between the I/O ports.
For an integrated citrcuit, however, the signal loss per millimeter transmission line length is much larger in silicon than for example in a PTFE printed circuit board or a ceramic chip package. This is particularly true for signals at high bitrate of 10 Gbit/s or more. It is therefore mandatory, to keep the signal paths on the chips as short as possible. As a general rule, amplitude regeneration is necessary after each 2 mm signal path length on a chip. This requirement limits the maximum chip size, since each buffer amplifier adds some jitter to the output signal. On the other hand, it is preferable to have as many inputs and outputs on a single chip as possible. Obviously, this latter aim leads to larger chips the higher the number of inputs and outputs. In particular, the number of crosspoints and thus the chip size scales quadratic with the number of inputs and outputs.
It is therefore an object of the present invention to provide an integrated electrical switching matrix for high bitrate applications of 10 Gbit/s or more with increased number of inputs and outputs.